/* pic18fxx8.h
   Header file for the Microchip controllers,

	pic18F248
	pic18F258
	pic18F448
	pic18F458
*/


// Special Function Registers

#byte	TOSU		= 0xFFF
#byte	TOSH		= 0xFFE
#byte	TOSL		= 0xFFD
#byte	STKPTR		= 0xFFC
#byte	PCLATU		= 0xFFB
#byte	PCLATH		= 0xFFA
#byte	PCL		= 0xFF9
#byte TBLPTR		= 0xFF6
#byte	TBLPTRU		= 0xFF8
#byte	TBLPTRH		= 0xFF7
#byte	TBLPTRL		= 0xFF6
#byte	TABLAT		= 0xFF5
#byte	PRODH		= 0xFF4
#byte	PRODL		= 0xFF3
#byte	INTCON		= 0xFF2
#byte	INTCON2		= 0xFF1
#byte	INTCON3		= 0xFF0
#byte	INDF0		= 0xFEF
#byte	POSTINC0	= 0xFEE
#byte	POSTDEC0	= 0xFED
#byte	PREINC0		= 0xFEC
#byte	PLUSW0		= 0xFEB
#byte	FSR0H		= 0xFEA
#byte	FSR0L		= 0xFE9
#byte	WREG		= 0xFE8
#byte	INDF1		= 0xFE7
#byte	POSTINC1	= 0xFE6
#byte	POSTDEC1	= 0xFE5
#byte	PREINC1		= 0xFE4
#byte	PLUSW1		= 0xFE3
#byte	FSR1H		= 0xFE2
#byte	FSR1L		= 0xFE1
#byte	BSR		= 0xFE0
#byte	INDF2		= 0xFDF
#byte	POSTINC2	= 0xFDE
#byte	POSTDEC2	= 0xFDD
#byte	PREINC2		= 0xFDC
#byte	PLUSW2		= 0xFDB
#byte	FSR2H		= 0xFDA
#byte	FSR2L		= 0xFD9
#byte	STATUS		= 0xFD8
#byte	TMR0		= 0xFD6
#byte	TMR0H		= 0xFD7
#byte	TMR0L		= 0xFD6
#byte	T0CON		= 0xFD5
#byte	OSCCON		= 0xFD3
#byte	LVDCON		= 0xFD2
#byte	WDTCON		= 0xFD1
#byte	RCON		= 0xFD0
#byte	TMR1		= 0xFCE
#byte	TMR1H		= 0xFCF
#byte	TMR1L		= 0xFCE
#byte	T1CON		= 0xFCD
#byte	TMR2		= 0xFCC
#byte	PR2		= 0xFCB
#byte	T2CON		= 0xFCA
#byte	SSPBUF		= 0xFC9
#byte	SSPADD		= 0xFC8
#byte	SSPSTAT		= 0xFC7
#byte	SSPCON1		= 0xFC6
#byte	SSPCON2		= 0xFC5
#byte	ADRES		= 0xFC3
#byte	ADRESH		= 0xFC4
#byte	ADRESL		= 0xFC3
#byte	ADCON0		= 0xFC2
#byte	ADCON1		= 0xFC1
#byte	CCPR1		= 0xFBE
#byte	CCPR1H		= 0xFBF
#byte	CCPR1L		= 0xFBE
#byte	CCP1CON		= 0xFBD
#if defined(_18F448) || defined(_18F458)
#byte	ECCPR1		= 0xFBB
#byte	ECCPR1H		= 0xFBC
#byte	ECCPR1L		= 0xFBB
#byte	ECCP1CON	= 0xFBA
#byte	ECCP1DEL	= 0xFB7
#byte	ECCPAS		= 0xFB6
#byte	CVRCON		= 0xFB5
#byte	CMCON		= 0xFB4
#endif
#byte	TMR3		= 0xFB2
#byte	TMR3H		= 0xFB3
#byte	TMR3L		= 0xFB2
#byte	T3CON		= 0xFB1
#if defined(_18F448) || defined(_18F458)
#byte	PSPCON		= 0xFB0
#endif
#byte	SPBRG		= 0xFAF
#byte	RCREG		= 0xFAE
#byte	TXREG		= 0xFAD
#byte	TXSTA		= 0xFAC
#byte	RCSTA		= 0xFAB
#byte	EEADR		= 0xFA9
#byte	EEDATA		= 0xFA8
#byte	EECON2		= 0xFA7
#byte	EECON1		= 0xFA6
#byte	IPR3		= 0xFA5
#byte	PIR3		= 0xFA4
#byte	PIE3		= 0xFA3
#byte	IPR2		= 0xFA2
#byte	PIR2		= 0xFA1
#byte	PIE2		= 0xFA0
#byte	IPR1		= 0xF9F
#byte	PIR1		= 0xF9E
#byte	PIE1		= 0xF9D
#if defined(_18F448) || defined(_18F458)
#byte	TRISE		= 0xF96
#byte	TRISD		= 0xF95
#endif
#byte	TRISC		= 0xF94
#byte	TRISB		= 0xF93
#byte	TRISA		= 0xF92
#if defined(_18F448) || defined(_18F458)
#byte	LATE		= 0xF8D
#byte	LATD		= 0xF8C
#endif
#byte	LATC		= 0xF8B
#byte	LATB		= 0xF8A
#byte	LATA		= 0xF89
#if defined(_18F448) || defined(_18F458)
#byte	PORTE		= 0xF84
#byte	PORTD		= 0xF83
#endif
#byte	PORTC		= 0xF82
#byte	PORTB		= 0xF81
#byte	PORTA		= 0xF80
#byte	TXERRCNT	= 0xF76
#byte	RXERRCNT	= 0xF75

// DEFINICIONES INCLUIDAS EN CAN-18xxx8.H

//#byte	COMSTAT		= 0xF74
//#byte	CIOCON		= 0xF73
//#byte	BRGCON3		= 0xF72
//#byte	BRGCON2		= 0xF71
//#byte	BRGCON1		= 0xF70


/*
#byte	CANCON		= 0xF6F
#byte	CANSTAT		= 0xF6E
#byte	RXB0D7		= 0xF6D
#byte	RXB0D6		= 0xF6C
#byte	RXB0D5		= 0xF6B
#byte	RXB0D4		= 0xF6A
#byte	RXB0D3		= 0xF69
#byte	RXB0D2		= 0xF68
#byte	RXB0D1		= 0xF67
#byte	RXB0D0		= 0xF66
#byte	RXB0DLC		= 0xF65
#byte	RXB0EIDL		= 0xF64
#byte	RXB0EIDH		= 0xF63
#byte	RXB0SIDL		= 0xF62
#byte	RXB0SIDH		= 0xF61
#byte	RXB0CON		= 0xF60
#byte	CANSTATRO1	= 0xF5E
#byte	RXB1D7		= 0xF5D
#byte	RXB1D6		= 0xF5C
#byte	RXB1D5		= 0xF5B
#byte	RXB1D4		= 0xF5A
#byte	RXB1D3		= 0xF59
#byte	RXB1D2		= 0xF58
#byte	RXB1D1		= 0xF57
#byte	RXB1D0		= 0xF56
#byte	RXB1DLC		= 0xF55
#byte	RXB1EIDL		= 0xF54
#byte	RXB1EIDH		= 0xF53
#byte	RXB1SIDL		= 0xF52
#byte	RXB1SIDH		= 0xF51
#byte	RXB1CON		= 0xF50
#byte	CANSTATRO2	= 0xF4E
#byte	TXB0D7		= 0xF4D
#byte	TXB0D6		= 0xF4C
#byte	TXB0D5		= 0xF4B
#byte	TXB0D4		= 0xF4A
#byte	TXB0D3		= 0xF49
#byte	TXB0D2		= 0xF48
#byte	TXB0D1		= 0xF47
#byte	TXB0D0		= 0xF46
#byte	TXB0DLC		= 0xF45
#byte	TXB0EIDL		= 0xF44
#byte	TXB0EIDH		= 0xF43
#byte	TXB0SIDL		= 0xF42
#byte	TXB0SIDH		= 0xF41
#byte	TXB0CON		= 0xF40
#byte	CANSTATRO3	= 0xF3E
#byte	TXB1D7		= 0xF3D
#byte	TXB1D6		= 0xF3C
#byte	TXB1D5		= 0xF3B
#byte	TXB1D4		= 0xF3A
#byte	TXB1D3		= 0xF39
#byte	TXB1D2		= 0xF38
#byte	TXB1D1		= 0xF37
#byte	TXB1D0		= 0xF36
#byte	TXB1DLC		= 0xF35
#byte	TXB1EIDL		= 0xF34
#byte	TXB1EIDH		= 0xF33
#byte	TXB1SIDL		= 0xF32
#byte	TXB1SIDH		= 0xF31
#byte	TXB1CON		= 0xF30
#byte	CANSTATRO4	= 0xF2E
#byte	TXB2D7		= 0xF2D
#byte	TXB2D6		= 0xF2C
#byte	TXB2D5		= 0xF2B
#byte	TXB2D4		= 0xF2A
#byte	TXB2D3		= 0xF29
#byte	TXB2D2		= 0xF28
#byte	TXB2D1		= 0xF27
#byte	TXB2D0		= 0xF26
#byte	TXB2DLC		= 0xF25
#byte	TXB2EIDL		= 0xF24
#byte	TXB2EIDH		= 0xF23
#byte	TXB2SIDL		= 0xF22
#byte	TXB2SIDH		= 0xF21
#byte	TXB2CON		= 0xF20
#byte	RXM1EIDL		= 0xF1F
#byte	RXM1EIDH		= 0xF1E
#byte	RXM1SIDL		= 0xF1D
#byte	RXM1SIDH		= 0xF1C
#byte	RXM0EIDL		= 0xF1B
#byte	RXM0EIDH		= 0xF1A
#byte	RXM0SIDL		= 0xF19
#byte	RXM0SIDH		= 0xF18
#byte	RXF5EIDL		= 0xF17
#byte	RXF5EIDH		= 0xF16
#byte	RXF5SIDL		= 0xF15
#byte	RXF5SIDH		= 0xF14
#byte	RXF4EIDL		= 0xF13
#byte	RXF4EIDH		= 0xF12
#byte	RXF4SIDL		= 0xF11
#byte	RXF4SIDH		= 0xF10
#byte	RXF3EIDL		= 0xF0F
#byte	RXF3EIDH		= 0xF0E
#byte	RXF3SIDL		= 0xF0D
#byte	RXF3SIDH		= 0xF0C
#byte	RXF2EIDL		= 0xF0B
#byte	RXF2EIDH		= 0xF0A
#byte	RXF2SIDL		= 0xF09
#byte	RXF2SIDH		= 0xF08
#byte	RXF1EIDL		= 0xF07
#byte	RXF1EIDH		= 0xF06
#byte	RXF1SIDL		= 0xF05
#byte	RXF1SIDH		= 0xF04
#byte	RXF0EIDL		= 0xF03
#byte	RXF0EIDH		= 0xF02
#byte	RXF0SIDL		= 0xF01
#byte RXF0SIDH		= 0xF00
*/

//Defining individual bits
// STKPTR Register
#bit	STKFUL	= STKPTR.7	// stack full flag
#bit	STKUNF	= STKPTR.6	// stack underflow flag

// INTCON Register
#bit	GIE	= INTCON.7	// global interrupt enable
#bit	GIEH	= INTCON.7	// enable high priority interrupts
#bit	PEIE	= INTCON.6	// peripheral interrupt enable
#bit	GIEL	= INTCON.6	// enable low priority peripheral interrupts
#bit	TMR0IE	= INTCON.5	// TMR0 overflow interrupt enable
#bit	INT0IE	= INTCON.4	// external interrupt 0 enable
#bit	RBIE	= INTCON.3	// RB port change interrupt enable
#bit	TMR0IF	= INTCON.2	// TMR0 overflow interrupt flag
#bit	INT0IF	= INTCON.1	// external interrupt 0 flag
#bit	RBIF	= INTCON.0	// RB port change interrupt flag

// INTCON2 Register
#bit	RBPU	= INTCON2.7	// port B pull-up enable
#bit	INTEDG0	= INTCON2.6	// external interrupt 0 edge select
#bit	INTEDG1	= INTCON2.5	// external interrupt 1 edge select
#bit	TMR0IP	= INTCON2.2	// TMR0 overflow interrupt priority
#bit	RBIP	= INTCON2.0	// RB port change interrupt priority

// INTCON3 Register
#bit	INT1IP	= INTCON3.6	// external interrupt 1 priority
#bit	INT1IE	= INTCON3.3	// external interrupt 1 enable
#bit	INT1IF	= INTCON3.0	// external interrupt 1 flag

// STATUS Register
#bit	NEGATIVE = STATUS.4	// negative result
#bit	OV	= STATUS.3	// overflow status
#bit	ZERO	= STATUS.2	// zero result
#bit	DC	= STATUS.1	// digit carry
#bit	CARRY	= STATUS.0	// carry/borrow

// T0CON Register
#bit	TMR0ON	= T0CON.7	// TMR0 on/off
#bit	T08BIT	= T0CON.6	// 8/16 bit select
#bit	T0CS	= T0CON.5	// TMR0 Source Select
#bit	T0SE	= T0CON.4	// TMR0 Source Edge Select
#bit	PSA	= T0CON.3	// Prescaler Assignment
#bit	T0PS2	= T0CON.2	// Prescaler
#bit	T0PS1	= T0CON.1
#bit	T0PS0	= T0CON.0

// OSCCON Register
#bit	SCS	= OSCCON.0	// system clock switch bit

// LVDCON Register
#bit	IRVST	= LVDCON.5	// input reference voltage stable status
#bit	LVDEN	= LVDCON.4	// low voltage detect enable
#bit	LVDL3	= LVDCON.3	// low voltage detection limits
#bit	LVDL2	= LVDCON.2
#bit	LVDL1	= LVDCON.1
#bit	LVDL0	= LVDCON.0

// WDTCON Register
#bit	SWDTEN	= WDTCON.0	// software watchdog timer enable

// RCON Register
#bit	IPEN	= RCON.7	// interrupt priority enable
#bit	RI	= RCON.4	// RESET instruction status
#bit	TO	= RCON.3	// watchdog timeout flag
#bit	PD	= RCON.2	// power-down detection
#bit	POR	= RCON.1	// power-on reset status
#bit	BOR	= RCON.0	// brown-our reset status

// T1CON Register
#bit	RD16	= T1CON.7	// 16 Bit Read/Write Enable
#bit	T1RD16	= T1CON.7	// 16 Bit Read/Write Enable
#bit	T1CKPS1	= T1CON.5	// Prescaler
#bit	T1CKPS0	= T1CON.4
#bit	T1OSCEN	= T1CON.3	// Oscillator Enable
#bit	T1SYNC	= T1CON.2	// Sync Selct
#bit	TMR1CS	= T1CON.1	// TMR Clock Source Select
#bit	TMR1ON	= T1CON.0	// TMR on/off

// T2CON Register
#bit	TOUTPS3	= T2CON.6	// Postscale
#bit	TOUTPS2	= T2CON.5
#bit	TOUTPS1	= T2CON.4
#bit	TOUTPS0	= T2CON.3
#bit	TMR2ON	= T2CON.2	// TMR2 On/Off
#bit	T2CKPS1	= T2CON.1	// Prescale
#bit	T2CKPS0	= T2CON.0

// SSPSTAT Register
#bit	SMP	= SSPSTAT.7	// Sample Bit
#bit	CKE	= SSPSTAT.6	// SPI Clk Edge Select
#bit	DA	= SSPSTAT.5	// Data/Address Bit
#bit	STOP	= SSPSTAT.4	// STOP Bit detected
#bit	START	= SSPSTAT.3	// START Bit detected
#bit	RW	= SSPSTAT.2	// Read/Write bit Information
#bit	UA	= SSPSTAT.1	// Update Adress
#bit	BF	= SSPSTAT.0	// Buffer Full Status bit

// SSPCON1 Register
#bit	WCOL	= SSPCON1.7	// write collision detect
#bit	SSPOV	= SSPCON1.6	// recieve overflow indicator
#bit	SSPEN	= SSPCON1.5	// SSP enable
#bit	CKP	= SSPCON1.4	// clock polarity select
#bit	SSPM3	= SSPCON1.3	// SSP mode select
#bit	SSPM2	= SSPCON1.2
#bit	SSPM1	= SSPCON1.1
#bit	SSPM0	= SSPCON1.0

// SSPCON2 Register
#bit	GCEN	= SSPCON2.7	// general call enable
#bit	ACKSTAT	= SSPCON2.6	// acknowledge status bit
#bit	ACKDT	= SSPCON2.5	// acknowledge data bit
#bit	ACKEN	= SSPCON2.4	// acknowledge sequence enable
#bit	RCEN	= SSPCON2.3	// recieve enable bit
#bit	PEN	= SSPCON2.2	// STOP condition enable
#bit	RSEN	= SSPCON2.1	// repeated START enable
#bit	SEN	= SSPCON2.0	// START condition enable

// ADCON0 Register
#bit	ADCS1	= ADCON0.7	// AD conv. clock select bits
#bit	ADCS0	= ADCON0.6
#bit	CHS2	= ADCON0.5	// channel select
#bit	CHS1	= ADCON0.4
#bit	CHS0	= ADCON0.3
#bit	GODONE	= ADCON0.2	// AD conversion status
#bit	ADON	= ADCON0.0	// AD on status

// ADCON1 Register
#bit	ADFM	= ADCON1.7	// AD result format
#bit	ADCS2	= ADCON1.6	// AD conv. clock select bits
#bit	PCGF3	= ADCON1.3	// AD port config bits
#bit	PCGF2	= ADCON1.2
#bit	PCFG1	= ADCON1.1
#bit	PCFG0	= ADCON1.0

// CCP1CON Register
#bit	DC1B1	= CCP1CON.5	// Duty Cycle Bits 1 & 0
#bit	DC1B0	= CCP1CON.4
#bit	CCP1M3	= CCP1CON.3	// Mode Select Bits
#bit	CCP1M2	= CCP1CON.2
#bit	CCP1M1	= CCP1CON.1
#bit	CCP1M0	= CCP1CON.0

#if defined(_18F448) || defined(_18F458)
// ECCP1CON Register
#bit	EPWM1M1	= ECCP1CON.7	// PWM output config bits
#bit	EPWM1M0	= ECCP1CON.6
#bit	EDC1B1	= ECCP1CON.5	// PWM duty cycle LSBs
#bit	EDC1B0	= ECCP1CON.4
#bit	ECCP1M3	= ECCP1CON.3	// EEPC1 mode select bits
#bit	ECCP1M2	= ECCP1CON.2
#bit	ECCP1M1	= ECCP1CON.1
#bit	ECCP1M0	= ECCP1CON.0

// ECCP1DEL Register
#bit	EPDC7	= ECCP1DEL.7	// PWM delay
#bit	EPDC6	= ECCP1DEL.6
#bit	EPDC5	= ECCP1DEL.5
#bit	EPDC4	= ECCP1DEL.4
#bit	EPDC3	= ECCP1DEL.3
#bit	EPDC2	= ECCP1DEL.2
#bit	EPDC1	= ECCP1DEL.1
#bit	EPDC0	= ECCP1DEL.0

// ECCPAS Register
#bit	ECCPASE	= ECCPAS.7	// ECCP auto-shutdown event status
#bit	ECCPAS2	= ECCPAS.6	// EECP auto-shutdown bits
#bit	ECCPAS1	= ECCPAS.5
#bit	ECCPAS0	= ECCPAS.4
#bit	PSSAC1	= ECCPAS.3	// pin A & C auto-shutdown control
#bit	PSSAC0	= ECCPAS.2
#bit	PCCBD1	= ECCPAS.1	// pin B & D auto-shutdown control
#bit	PCCBD0	= ECCPAS.0

// CVRCON Register
#bit	CVREN	= CVRCON.7	// comparator voltage reference enable
#bit	CVROE	= CVRCON.6	// comparator VREF output enable
#bit	CVRR	= CVRCON.5	// comparator VREF range select
#bit	CVRSS	= CVRCON.4	// comparator VREF source select
#bit	CVR3	= CVRCON.3	// comparator VREF value selection
#bit	CVR2	= CVRCON.2
#bit	CVR1	= CVRCON.1
#bit	CVR0	= CVRCON.0

// CMCON Comparator module register
//#bit	C2OUT	= CMCON.7	// comparator 2 output
//#bit	C1OUT	= CMCON.6	// comparator 1 output
//#bit	C2INV	= CMCON.5	// select to invert comp2 output
//#bit	C1INV	= CMCON.4	// select to invert comp1 output
//#bit	CIS	= CMCON.3	// comp input switch bit
//#bit	CM2	= CMCON.2	// comp mode select bits
//#bit	CM1	= CMCON.1
//#bit	CM0	= CMCON.0
#endif

// T3CON Register
#bit	T3RD16	= T3CON.7	// 16-Bit Read/Write select
#bit	T3ECCP1	= T3CON.6	// TMR3 & TMR1 CCPx Enable
#bit	T3CKPS1	= T3CON.5	// Prescaler
#bit	T3CKPS0	= T3CON.4
#bit	T3CCP1	= T3CON.3	// TMR3 & TMR1 CCPx Enable
#bit	T3SYNC	= T3CON.2	// Sync Select
#bit	TMR3CS	= T3CON.1	// TMR3 source Select
#bit	TMR3ON	= T3CON.0	// TMR3 on/off

#if defined(_18F448) || defined(_18F458)
// PSPCON Register
#bit	IBF	= PSPCON.7	// input buffer full status
#bit	OBF	= PSPCON.6	// output buffer full status
#bit	IBOV	= PSPCON.5	// input buffer overflow
#bit	PSPMODE	= PSPCON.4	// parallel slave port mode select
#endif

// TXSTA Register
#bit	CSRC	= TXSTA.7	// CLK source select
#bit	TX9	= TXSTA.6	// 8/9 bit TX data select
#bit	TXEN	= TXSTA.5	// transmit enable bit
#bit	SYNC	= TXSTA.4	// USART mode select
#bit	BRGH	= TXSTA.2	// high baud rate select
#bit	TRMT	= TXSTA.1	// TX shift reg. status bit
#bit	TX9D	= TXSTA.0	// 9th Bit of TX data

// RCSTA Register
#bit	SPEN	= RCSTA.7	// serial port enable
#bit	RX9	= RCSTA.6	// 8/9 bit data reception
#bit	SREN	= RCSTA.5	// single recieve enable
#bit	CREN	= RCSTA.4	// continuous recieve enable
#bit	ADDEN	= RCSTA.3	// address detect enable
#bit	FERR	= RCSTA.2	// framing error
#bit	OERR	= RCSTA.1	// overrun error
#bit	RX9D	= RCSTA.0	// 9th Bit of RX data

// EECON1 Register
#bit	EEPGD	= EECON1.7	// FLASH/EEPROM select
#bit	EEFS	= EECON1.6	// access config regs./access FLASH-EEPROM
// alternate definition
#bit	CFGS	= EECON1.6 	//Config./Calibration Select
#bit	FREE	= EECON1.4	// FLASH row erase enable
#bit	WRERR	= EECON1.3	// write error flag
#bit	WREN	= EECON1.2	// write enable
#bit	WR	= EECON1.1	// write control
#bit	RD	= EECON1.0	// read control

// IPR3 Register
#bit 	IRXIP	= IPR3.7	// CAN invalid rec. message interrupt priority
#bit 	WAKIP	= IPR3.6	// CANbus activity wake-up interrupt priority
#bit 	ERRIP	= IPR3.5	// CANbus error interrupt priority
#bit 	TXB2IP	= IPR3.4	// CAN TX buffer 2 interrupt priority
#bit 	TXB1IP	= IPR3.3	// CAN TX buffer 1 interrupt priority
#bit 	TXB0IP	= IPR3.2	// CAN TX buffer 0 interrupt priority
#bit 	RXB1IP	= IPR3.1	// CAN RX buffer 1 interrupt priority
#bit 	RXB0IP	= IPR3.0	// CAN RX buffer 0 interrupt priority

// PIR3 Register
#bit	IRXIF	= PIR3.7	// CAN invalid rec. message interrupt flag
#bit	WAKIF	= PIR3.6	// CANbus activity wake-up interrupt flag
#bit	ERRIF	= PIR3.5	// CANbus error interrupt flag
#bit	TXB2IF	= PIR3.4	// CAN TX buffer 2 interrupt flag
#bit	TXB1IF	= PIR3.3	// CAN TX buffer 1 interrupt flag
#bit	TXB0IF	= PIR3.2	// CAN TX buffer 0 interrupt flag
#bit	RXB1IF	= PIR3.1	// CAN RX buffer 1 interrupt flag
#bit	RXB0IF	= PIR3.0	// CAN RX buffer 0 interrupt flag

// PIE3 Register
#bit 	IRXIE  	= PIE3.7	// CAN invalid rec. message interrupt enable
#bit 	WAKIE  	= PIE3.6	// CANbus activity wake-up interrupt enable
#bit 	ERRIE  	= PIE3.5	// CANbus error interrupt enable
#bit 	TXB2IE	= PIE3.4	// CAN TX buffer 2 interrupt enable
#bit 	TXB1IE	= PIE3.3	// CAN TX buffer 1 interrupt enable
#bit 	TXB0IE	= PIE3.2	// CAN TX buffer 0 interrupt enable
#bit 	RXB1IE	= PIE3.1	// CAN RX buffer 1 interrupt enable
#bit 	RXB0IE	= PIE3.0	// CAN RX buffer 0 interrupt enable

// IPR2 Register
#bit 	CMIP	= IPR2.6	// comparator interrupt priority
#bit 	EEIP	= IPR2.4	// EEPROM write interrupt priority
#bit 	BCLIP	= IPR2.3	// bus collision interrupt priority
#bit 	LVDIP	= IPR2.2	// low voltage detect interrupt priority
#bit 	TMR3IP	= IPR2.1	// TMR3 overflow interrupt priority
#if defined(_18F448) || defined(_18F458)
#bit 	ECCP1IP	= IPR2.0	// ECCP1 interrupt priority
#endif

// PIR2 Register
#bit	CMIF 	= PIR2.6	// comparator interrupt flag
#bit	EEIF 	= PIR2.4	// EEPROM write interrupt flag
#bit	BCLIF 	= PIR2.3	// bus collision interrupt flag
#bit	LVDIF 	= PIR2.2	// low voltage detect interrupt flag
#bit	TMR3IF 	= PIR2.1	// TMR3 overflow interrupt flag
#if defined(_18F448) || defined(_18F458)
#bit	ECCP1IF	= PIR2.0	// ECCP1 interrupt flag
#endif

// PIE2 Register
#bit 	CMIE 	= PIE2.6	// comparator interrupt enable
#bit 	EEIE 	= PIE2.4	// EEPROM write interrupt enable
#bit 	BCLIE 	= PIE2.3	// bus collision interrupt enable
#bit 	LVDIE 	= PIE2.2	// low voltage detect interrupt enable
#bit 	TMR3IE 	= PIE2.1	// TMR3 overflow interrupt enable
#if defined(_18F448) || defined(_18F458)
#bit 	ECCP1IE	= PIE2.0	// ECCP1 interrupt enable
#endif

// IPR1 Register
#if defined(_18F448) || defined(_18F458)
#bit 	PSPIP	= IPR1.7	// para. slave port rd/wr interrupt priority
#endif
#bit 	ADIP	= IPR1.6	// AD conv. interrupt priority
#bit 	RCIP	= IPR1.5	// USART RX interrupt priority
#bit 	TXIP	= IPR1.4	// USART TX interrupt priority
#bit 	SSPIP	= IPR1.3	// master SSP interrupt priority
#bit 	CCP1IP	= IPR1.2	// CCP1 interrupt priority
#bit 	TMR2IP	= IPR1.1	// TMR2 - PR2 match interrupt priority
#bit 	TMR1IP	= IPR1.0	// TMR1 overflow interrupt priority

// PIR1 Register
#if defined(_18F448) || defined(_18F458)
#bit	PSPIF  	= PIR1.7	// para. slave port rd/wr interrupt flag
#endif
#bit	ADIF  	= PIR1.6	// AD conv. interrupt flag
#bit	RCIF  	= PIR1.5	// USART RX interrupt flag
#bit	TXIF  	= PIR1.4	// USART TX interrupt flag
#bit	SSPIF  	= PIR1.3	// master SSP interrupt flag
#bit	CCP1IF	= PIR1.2	// CCP1 interrupt flag
#bit	TMR2IF	= PIR1.1	// TMR2 - PR2 match interrupt flag
#bit	TMR1IF	= PIR1.0	// TMR1 overflow interrupt flag

// PIE1 Register
#if defined(_18F448) || defined(_18F458)
#bit 	PSPIE  	= PIE1.7	// para. slave port rd/wr interrupt enable
#endif
#bit 	ADIE  	= PIE1.6	// AD conv. interrupt enable
#bit 	RCIE  	= PIE1.5	// USART RX interrupt enable
#bit 	TXIE  	= PIE1.4	// USART TX interrupt enable
#bit 	SSPIE  	= PIE1.3	// master SSP interrupt enable
#bit 	CCP1IE	= PIE1.2	// CCP1 interrupt enable
#bit 	TMR2IE	= PIE1.1	// TMR2 - PR2 match interrupt enable
#bit 	TMR1IE	= PIE1.0	// TMR1 overflow interrupt enable

#if defined(_18F448) || defined(_18F458)
// TRISE Register
#bit	TRISE2	= TRISE.2	// port E data direction
#bit	TRISE1	= TRISE.1
#bit	TRISE0	= TRISE.0

// TRISD Register
#bit 	TRISD7	= TRISD.7	// port D data direction
#bit 	TRISD6	= TRISD.6
#bit 	TRISD5	= TRISD.5
#bit 	TRISD4	= TRISD.4
#bit 	TRISD3	= TRISD.3
#bit 	TRISD2	= TRISD.2
#bit 	TRISD1	= TRISD.1
#bit 	TRISD0	= TRISD.0
#endif

// TRISC Register
#bit 	TRISC7	= TRISC.7	// port C data direction
#bit 	TRISC6	= TRISC.6
#bit 	TRISC5	= TRISC.5
#bit 	TRISC4	= TRISC.4
#bit 	TRISC3	= TRISC.3
#bit 	TRISC2	= TRISC.2
#bit 	TRISC1	= TRISC.1
#bit 	TRISC0	= TRISC.0

// TRISB Register
#bit 	TRISB7	= TRISB.7	// port B data direction
#bit 	TRISB6	= TRISB.6
#bit 	TRISB5	= TRISB.5
#bit 	TRISB4	= TRISB.4
#bit 	TRISB3	= TRISB.3
#bit 	TRISB2	= TRISB.2
#bit 	TRISB1	= TRISB.1
#bit 	TRISB0	= TRISB.0

// TRISA Register
#bit 	TRISA7	= TRISA.7	// port A data direction
#bit 	TRISA6	= TRISA.6
#bit 	TRISA5	= TRISA.5
#bit 	TRISA4	= TRISA.4
#bit 	TRISA3	= TRISA.3
#bit 	TRISA2	= TRISA.2
#bit 	TRISA1	= TRISA.1
#bit 	TRISA0	= TRISA.0

#if defined(_18F448) || defined(_18F458)
// LATE Register
#bit	LATE2	= LATE.2	// port E data latch
#bit	LATE1	= LATE.1
#bit	LATE0	= LATE.0

// LATD Register
#bit 	LATD7	= LATD.7	// port D data latch
#bit 	LATD6	= LATD.6
#bit 	LATD5	= LATD.5
#bit 	LATD4	= LATD.4
#bit 	LATD3	= LATD.3
#bit 	LATD2	= LATD.2
#bit 	LATD1	= LATD.1
#bit 	LATD0	= LATD.0
#endif

// LATC Register
#bit 	LATC7	= LATC.7	// port C data latch
#bit 	LATC6	= LATC.6
#bit 	LATC5	= LATC.5
#bit 	LATC4	= LATC.4
#bit 	LATC3	= LATC.3
#bit 	LATC2	= LATC.2
#bit 	LATC1	= LATC.1
#bit 	LATC0	= LATC.0

// LATB Register
#bit 	LATB7	= LATB.7	// port B data latch
#bit 	LATB6	= LATB.6
#bit 	LATB5	= LATB.5
#bit 	LATB4	= LATB.4
#bit 	LATB3	= LATB.3
#bit 	LATB2	= LATB.2
#bit 	LATB1	= LATB.1
#bit 	LATB0	= LATB.0

// LATA Register
#bit 	LATA7	= LATA.7	// port A data latch
#bit 	LATA6	= LATA.6
#bit 	LATA5	= LATA.5
#bit 	LATA4	= LATA.4
#bit 	LATA3	= LATA.3
#bit 	LATA2	= LATA.2
#bit 	LATA1	= LATA.1
#bit 	LATA0	= LATA.0

#if defined(_18F448) || defined(_18F458)
// PORTE Register
#bit	RE2	= PORTE.2
#bit	RE1	= PORTE.1
#bit	RE0	= PORTE.0

// PORTD Register
#bit	RD7	= PORTD.7
#bit	RD6	= PORTD.6
#bit	RD5	= PORTD.5
#bit	RD4	= PORTD.4
#bit	RD3	= PORTD.3
#bit	RD2	= PORTD.2
#bit	RD1	= PORTD.1
#bit	RD0	= PORTD.0
#endif

// PORTC Register
#bit	RC7	= PORTC.7
#bit	RC6	= PORTC.6
#bit	RC5	= PORTC.5
#bit	RC4	= PORTC.4
#bit	RC3	= PORTC.3
#bit	RC2	= PORTC.2
#bit	RC1	= PORTC.1
#bit	RC0	= PORTC.0

// PORTB Register
#bit	RB7	= PORTB.7
#bit	RB6	= PORTB.6
#bit	RB5	= PORTB.5
#bit	RB4	= PORTB.4
#bit	RB3	= PORTB.3
#bit	RB2	= PORTB.2
#bit	RB1	= PORTB.1
#bit	RB0	= PORTB.0

// PORTA Register
#bit	RA7	= PORTA.7
#bit	RA6	= PORTA.6
#bit	RA5	= PORTA.5
#bit	RA4	= PORTA.4
#bit	RA3	= PORTA.3
#bit	RA2	= PORTA.2
#bit	RA1	= PORTA.1
#bit	RA0	= PORTA.0

// TXERRCNT Register
#bit	TEC7	= TXERRCNT.7	// TX error count bits
#bit	TEC6	= TXERRCNT.6
#bit	TEC5	= TXERRCNT.5
#bit	TEC4	= TXERRCNT.4
#bit	TEC3	= TXERRCNT.3
#bit	TEC2	= TXERRCNT.2
#bit	TEC1	= TXERRCNT.1
#bit	TEC0	= TXERRCNT.0

// RXERRCNT Register
#bit	REC7	= RXERRCNT.7	// RX error count bits
#bit	REC6	= RXERRCNT.6
#bit	REC5	= RXERRCNT.5
#bit	REC4	= RXERRCNT.4
#bit	REC3	= RXERRCNT.3
#bit	REC2	= RXERRCNT.2
#bit	REC1	= RXERRCNT.1
#bit	REC0	= RXERRCNT.0



/*
// COMSTAT Register
#bit	RXB0OVFL	= COMSTAT.7	// RX buffer 0 overflow
#bit	RXB1OVFL	= COMSTAT.6	// RX buffer 1 overflow
#bit	TXBO		= COMSTAT.5	// TX bus off
#bit	TXBP		= COMSTAT.4	// TX bus passive bit
#bit	RXBP		= COMSTAT.3	// RX bus passive bit
#bit	TXWARN		= COMSTAT.2	// transmitter warning
#bit	RXWARN		= COMSTAT.1	// reciever warning
#bit	EWARN		= COMSTAT.0	// error warning

// CIOCON Register
#bit	ENDRHI		= CIOCON.5	// enable drive high bit
#bit	CANCAP		= CIOCON.4	// CAN message rec. capture enable bit

// BRGCON3 Register
#bit	WAKFIL		= BRGCON3.6	// select CANbus line filter for wake-up bit
#bit	SEG2PH2		= BRGCON3.2	// phase segment 2 time select
#bit	SEG2PH1		= BRGCON3.1
#bit	SEG2PH0		= BRGCON3.0

// BRGCON2 Register
#bit	SEG2PHTS	= BRGCON2.7	// phase segment 2 time select
#bit	SAM		= BRGCON2.6	// sample of CANbus line bit
#bit	SEG1PH2		= BRGCON2.5	// phase segment 1 bits
#bit	SEG1PH1		= BRGCON2.4
#bit	SEG1PH0		= BRGCON2.3
#bit	PRSEG2		= BRGCON2.2	// propagation time select
#bit	PRSEG1		= BRGCON2.1
#bit	PRSEG0		= BRGCON2.0

// BRGCON1 Register
#bit	SJW1		= BRGCON1.7	// sync jump width bits
#bit	SJW0		= BRGCON1.6
#bit	BRP5		= BRGCON1.5	// baud rate prescaler
#bit	BRP4		= BRGCON1.4
#bit	BRP3		= BRGCON1.3
#bit	BRP2		= BRGCON1.2
#bit	BRP1		= BRGCON1.1
#bit	BRP0		= BRGCON1.0

// CANCON Register
#bit	REQOP2		= CANCON.7	// request CAN operation mode bits
#bit	REQOP1		= CANCON.6
#bit	REQOP0		= CANCON.5
#bit	ABAT		= CANCON.4	// abort all pendig transmissions
#bit	WIN2		= CANCON.3	// window address bits
#bit	WIN1		= CANCON.2
#bit	WIN0		= CANCON.1

// CANSTAT Register
#bit	OPMODE2		= CANSTAT.7	// operation mode bits
#bit	OPMODE1		= CANSTAT.6
#bit	OPMODE0		= CANSTAT.5
#bit	ICODE2		= CANSTAT.3	// interrupt code bits
#bit	ICODE1		= CANSTAT.2
#bit	ICODE0		= CANSTAT.1

// RXB0D7 Register
#bit	RXB0D77		= RXB0D7.7	// RX data
#bit	RXB0D76		= RXB0D7.6
#bit	RXB0D75		= RXB0D7.5
#bit	RXB0D74		= RXB0D7.4
#bit	RXB0D73		= RXB0D7.3
#bit	RXB0D72		= RXB0D7.2
#bit	RXB0D71		= RXB0D7.1
#bit	RXB0D70		= RXB0D7.0

// RXB0D6 Register
#bit	RXB0D67		= RXB0D6.7
#bit	RXB0D66		= RXB0D6.6
#bit	RXB0D65		= RXB0D6.5
#bit	RXB0D64		= RXB0D6.4
#bit	RXB0D63		= RXB0D6.3
#bit	RXB0D62		= RXB0D6.2
#bit	RXB0D61		= RXB0D6.1
#bit	RXB0D60		= RXB0D6.0

// RXB0D5 Register
#bit	RXB0D57		= RXB0D5.7
#bit	RXB0D56		= RXB0D5.6
#bit	RXB0D55		= RXB0D5.5
#bit	RXB0D54		= RXB0D5.4
#bit	RXB0D53		= RXB0D5.3
#bit	RXB0D52		= RXB0D5.2
#bit	RXB0D51		= RXB0D5.1
#bit	RXB0D50		= RXB0D5.0

// RXB0D4 Register
#bit	RXB0D47		= RXB0D4.7
#bit	RXB0D46		= RXB0D4.6
#bit	RXB0D45		= RXB0D4.5
#bit	RXB0D44		= RXB0D4.4
#bit	RXB0D43		= RXB0D4.3
#bit	RXB0D42		= RXB0D4.2
#bit	RXB0D41		= RXB0D4.1
#bit	RXB0D40		= RXB0D4.0

// RXB0D3 Register
#bit	RXB0D37		= RXB0D3.7
#bit	RXB0D36		= RXB0D3.6
#bit	RXB0D35		= RXB0D3.5
#bit	RXB0D34		= RXB0D3.4
#bit	RXB0D33		= RXB0D3.3
#bit	RXB0D32		= RXB0D3.2
#bit	RXB0D31		= RXB0D3.1
#bit	RXB0D30		= RXB0D3.0

// RXB0D2 Register
#bit	RXB0D27		= RXB0D2.7
#bit	RXB0D26		= RXB0D2.6
#bit	RXB0D25		= RXB0D2.5
#bit	RXB0D24		= RXB0D2.4
#bit	RXB0D23		= RXB0D2.3
#bit	RXB0D22		= RXB0D2.2
#bit	RXB0D21		= RXB0D2.1
#bit	RXB0D20		= RXB0D2.0

// RXB0D1 Register
#bit	RXB0D17		= RXB0D1.7
#bit	RXB0D16		= RXB0D1.6
#bit	RXB0D15		= RXB0D1.5
#bit	RXB0D14		= RXB0D1.4
#bit	RXB0D13		= RXB0D1.3
#bit	RXB0D12		= RXB0D1.2
#bit	RXB0D11		= RXB0D1.1
#bit	RXB0D10		= RXB0D1.0

// RXB0D0 Register
#bit	RXB0D07		= RXB0D0.7
#bit	RXB0D06		= RXB0D0.6
#bit	RXB0D05		= RXB0D0.5
#bit	RXB0D04		= RXB0D0.4
#bit	RXB0D03		= RXB0D0.3
#bit	RXB0D02		= RXB0D0.2
#bit	RXB0D01		= RXB0D0.1
#bit	RXB0D00		= RXB0D0.0

// RXB0DLC Register
#bit	RXB0RXRTR	= RXB0DLC.6
#bit	RXB0RB1		= RXB0DLC.5
#bit	RXB0RB0		= RXB0DLC.4
#bit	RXB0DLC3	= RXB0DLC.3
#bit	RXB0DLC2	= RXB0DLC.2
#bit	RXB0DLC1	= RXB0DLC.1
#bit	RXB0DLC0	= RXB0DLC.0

// RXB0EIDL Register
#bit	RXB0EID7	= RXB0EIDL.7
#bit	RXB0EID6	= RXB0EIDL.6
#bit	RXB0EID5	= RXB0EIDL.5
#bit	RXB0EID4	= RXB0EIDL.4
#bit	RXB0EID3	= RXB0EIDL.3
#bit	RXB0EID2	= RXB0EIDL.2
#bit	RXB0EID1	= RXB0EIDL.1
#bit	RXB0EID0	= RXB0EIDL.0

// RXB0EIDH Register
#bit	RXB0EID15	= RXB0EIDH.7
#bit	RXB0EID14	= RXB0EIDH.6
#bit	RXB0EID13	= RXB0EIDH.5
#bit	RXB0EID12	= RXB0EIDH.4
#bit	RXB0EID11	= RXB0EIDH.3
#bit	RXB0EID10	= RXB0EIDH.2
#bit	RXB0EID9	= RXB0EIDH.1
#bit	RXB0EID8	= RXB0EIDH.0

// RXB0SIDL Register
#bit	RXB0SID2	= RXB0SIDL.7
#bit	RXB0SID1	= RXB0SIDL.6
#bit	RXB0SID0	= RXB0SIDL.5
#bit	RXB0SRR		= RXB0SIDL.4
#bit	RXB0EXID	= RXB0SIDL.3
#bit	RXB0EID17	= RXB0SIDL.1
#bit	RXB0EID16	= RXB0SIDL.0

// RXB0SIDH Register
#bit	RXB0SID10	= RXB0SIDH.7
#bit	RXB0SID9	= RXB0SIDH.6
#bit	RXB0SID8	= RXB0SIDH.5
#bit	RXB0SID7	= RXB0SIDH.4
#bit	RXB0SID6	= RXB0SIDH.3
#bit	RXB0SID5	= RXB0SIDH.2
#bit	RXB0SID4	= RXB0SIDH.1
#bit	RXB0SID3	= RXB0SIDH.0

// RXB0CON Register
#bit	RXB0FUL		= RXB0CON.7	// recieve full status
#bit	RXB0M1		= RXB0CON.6	// RX buffer mode
#bit	RXB0M0		= RXB0CON.5
#bit	RXB0RTRRO	= RXB0CON.3	// RX remote transfer request
#bit	RXB0DBEN	= RXB0CON.2	// RX buffer, double buffer enable
#bit	JTOFF		= RXB0CON.1	// jump table offset
#bit	RXB0FILHIT0	= RXB0CON.0	// filter hit bit

// CANSTATRO1 Register
#bit	OPMODE12	= CANSTATRO1.7
#bit	OPMODE11	= CANSTATRO1.6
#bit	OPMODE10	= CANSTATRO1.5
#bit	ICODE12		= CANSTATRO1.3
#bit	ICODE11		= CANSTATRO1.2
#bit	ICODE10		= CANSTATRO1.1

// RXB1D7 Register
#bit	RXB1D77		= RXB1D7.7
#bit	RXB1D76		= RXB1D7.6
#bit	RXB1D75		= RXB1D7.5
#bit	RXB1D74		= RXB1D7.4
#bit	RXB1D73		= RXB1D7.3
#bit	RXB1D72		= RXB1D7.2
#bit	RXB1D71		= RXB1D7.1
#bit	RXB1D70		= RXB1D7.0

// RXB1D6 Register
#bit	RXB1D67		= RXB1D6.7
#bit	RXB1D66		= RXB1D6.6
#bit	RXB1D65		= RXB1D6.5
#bit	RXB1D64		= RXB1D6.4
#bit	RXB1D63		= RXB1D6.3
#bit	RXB1D62		= RXB1D6.2
#bit	RXB1D61		= RXB1D6.1
#bit	RXB1D60		= RXB1D6.0

// RXB1D5 Register
#bit	RXB1D57		= RXB1D5.7
#bit	RXB1D56		= RXB1D5.6
#bit	RXB1D55		= RXB1D5.5
#bit	RXB1D54		= RXB1D5.4
#bit	RXB1D53		= RXB1D5.3
#bit	RXB1D52		= RXB1D5.2
#bit	RXB1D51		= RXB1D5.1
#bit	RXB1D50		= RXB1D5.0

// RXB1D4 Register
#bit	RXB1D47		= RXB1D4.7
#bit	RXB1D46		= RXB1D4.6
#bit	RXB1D45		= RXB1D4.5
#bit	RXB1D44		= RXB1D4.4
#bit	RXB1D43		= RXB1D4.3
#bit	RXB1D42		= RXB1D4.2
#bit	RXB1D41		= RXB1D4.1
#bit	RXB1D40		= RXB1D4.0

// RXB1D3 Register
#bit	RXB1D37		= RXB1D3.7
#bit	RXB1D36		= RXB1D3.6
#bit	RXB1D35		= RXB1D3.5
#bit	RXB1D34		= RXB1D3.4
#bit	RXB1D33		= RXB1D3.3
#bit	RXB1D32		= RXB1D3.2
#bit	RXB1D31		= RXB1D3.1
#bit	RXB1D30		= RXB1D3.0

// RXB1D2 Register
#bit	RXB1D27		= RXB1D2.7
#bit	RXB1D26		= RXB1D2.6
#bit	RXB1D25		= RXB1D2.5
#bit	RXB1D24		= RXB1D2.4
#bit	RXB1D23		= RXB1D2.3
#bit	RXB1D22		= RXB1D2.2
#bit	RXB1D21		= RXB1D2.1
#bit	RXB1D20		= RXB1D2.0

// RXB1D1 Register
#bit	RXB1D17		= RXB1D1.7
#bit	RXB1D16		= RXB1D1.6
#bit	RXB1D15		= RXB1D1.5
#bit	RXB1D14		= RXB1D1.4
#bit	RXB1D13		= RXB1D1.3
#bit	RXB1D12		= RXB1D1.2
#bit	RXB1D11		= RXB1D1.1
#bit	RXB1D10		= RXB1D1.0

// RXB1D0 Register
#bit	RXB1D07		= RXB1D0.7
#bit	RXB1D06		= RXB1D0.6
#bit	RXB1D05		= RXB1D0.5
#bit	RXB1D04		= RXB1D0.4
#bit	RXB1D03		= RXB1D0.3
#bit	RXB1D02		= RXB1D0.2
#bit	RXB1D01		= RXB1D0.1
#bit	RXB1D00		= RXB1D0.0

// RXB1DLC Register
#bit	RXB1RXRTR	= RXB1DLC.6
#bit	RXB1RB1		= RXB1DLC.5
#bit	RXB1RB0		= RXB1DLC.4
#bit	RXB1DLC3	= RXB1DLC.3
#bit	RXB1DLC2	= RXB1DLC.2
#bit	RXB1DLC1	= RXB1DLC.1
#bit	RXB1DLC0	= RXB1DLC.0

// RXB1EIDL Register
#bit	RXB1EID7	= RXB1EIDL.7
#bit	RXB1EID6	= RXB1EIDL.6
#bit	RXB1EID5	= RXB1EIDL.5
#bit	RXB1EID4	= RXB1EIDL.4
#bit	RXB1EID3	= RXB1EIDL.3
#bit	RXB1EID2	= RXB1EIDL.2
#bit	RXB1EID1	= RXB1EIDL.1
#bit	RXB1EID0	= RXB1EIDL.0

// RXB1EIDH Register
#bit	RXB1EID15	= RXB1EIDH.7
#bit	RXB1EID14	= RXB1EIDH.6
#bit	RXB1EID13	= RXB1EIDH.5
#bit	RXB1EID12	= RXB1EIDH.4
#bit	RXB1EID11	= RXB1EIDH.3
#bit	RXB1EID10	= RXB1EIDH.2
#bit	RXB1EID9	= RXB1EIDH.1
#bit	RXB1EID8	= RXB1EIDH.0

// RXB1SIDL Register
#bit	RXB1SID2	= RXB1SIDL.7
#bit	RXB1SID1	= RXB1SIDL.6
#bit	RXB1SID0	= RXB1SIDL.5
#bit	RXB1SRR		= RXB1SIDL.4
#bit	RXB1EXID	= RXB1SIDL.3
#bit	RXB1EID17	= RXB1SIDL.1
#bit	RXB1EID16	= RXB1SIDL.0

// RXB1SIDH Register
#bit	RXB1SID10	= RXB1SIDH.7
#bit	RXB1SID9	= RXB1SIDH.6
#bit	RXB1SID8	= RXB1SIDH.5
#bit	RXB1SID7	= RXB1SIDH.4
#bit	RXB1SID6	= RXB1SIDH.3
#bit	RXB1SID5	= RXB1SIDH.2
#bit	RXB1SID4	= RXB1SIDH.1
#bit	RXB1SID3	= RXB1SIDH.0

// RXB1CON Register
#bit	RXB1FUL		= RXB1CON.7	// recieve full status
#bit	RXB1M1		= RXB1CON.6	// RX buffer mode
#bit	RXB1M0		= RXB1CON.5
#bit	RXB1RTRRO	= RXB1CON.3	// RX remote transmit request
#bit	RXB1FILHIT2	= RXB1CON.2	// filter hit bits
#bit	RXB1FILHIT1	= RXB1CON.1
#bit	RXB1FILHIT0	= RXB1CON.0

// CANSTATRO2 Register
#bit	OPMODE22	= CANSTATRO2.7
#bit	OPMODE21	= CANSTATRO2.6
#bit	OPMODE20	= CANSTATRO2.5
#bit	ICODE22		= CANSTATRO2.3
#bit	ICODE21		= CANSTATRO2.2
#bit	ICODE20		= CANSTATRO2.1

// TXB0D7 Register
#bit	TXB0D77		= TXB0D7.7
#bit	TXB0D76		= TXB0D7.6
#bit	TXB0D75		= TXB0D7.5
#bit	TXB0D74		= TXB0D7.4
#bit	TXB0D73		= TXB0D7.3
#bit	TXB0D72		= TXB0D7.2
#bit	TXB0D71		= TXB0D7.1
#bit	TXB0D70		= TXB0D7.0

// TXB0D6 Register
#bit	TXB0D67		= TXB0D6.7
#bit	TXB0D66		= TXB0D6.6
#bit	TXB0D65		= TXB0D6.5
#bit	TXB0D64		= TXB0D6.4
#bit	TXB0D63		= TXB0D6.3
#bit	TXB0D62		= TXB0D6.2
#bit	TXB0D61		= TXB0D6.1
#bit	TXB0D60		= TXB0D6.0

// TXB0D5 Register
#bit	TXB0D57		= TXB0D5.7
#bit	TXB0D56		= TXB0D5.6
#bit	TXB0D55		= TXB0D5.5
#bit	TXB0D54		= TXB0D5.4
#bit	TXB0D53		= TXB0D5.3
#bit	TXB0D52		= TXB0D5.2
#bit	TXB0D51		= TXB0D5.1
#bit	TXB0D50		= TXB0D5.0

// TXB0D4 Register
#bit	TXB0D47		= TXB0D4.7
#bit	TXB0D46		= TXB0D4.6
#bit	TXB0D45		= TXB0D4.5
#bit	TXB0D44		= TXB0D4.4
#bit	TXB0D43		= TXB0D4.3
#bit	TXB0D42		= TXB0D4.2
#bit	TXB0D41		= TXB0D4.1
#bit	TXB0D40		= TXB0D4.0

// TXB0D3 Register
#bit	TXB0D37		= TXB0D3.7
#bit	TXB0D36		= TXB0D3.6
#bit	TXB0D35		= TXB0D3.5
#bit	TXB0D34		= TXB0D3.4
#bit	TXB0D33		= TXB0D3.3
#bit	TXB0D32		= TXB0D3.2
#bit	TXB0D31		= TXB0D3.1
#bit	TXB0D30		= TXB0D3.0

// TXB0D2 Register
#bit	TXB0D27		= TXB0D2.7
#bit	TXB0D26		= TXB0D2.6
#bit	TXB0D25		= TXB0D2.5
#bit	TXB0D24		= TXB0D2.4
#bit	TXB0D23		= TXB0D2.3
#bit	TXB0D22		= TXB0D2.2
#bit	TXB0D21		= TXB0D2.1
#bit	TXB0D20		= TXB0D2.0

// TXB0D1 Register
#bit	TXB0D17		= TXB0D1.7
#bit	TXB0D16		= TXB0D1.6
#bit	TXB0D15		= TXB0D1.5
#bit	TXB0D14		= TXB0D1.4
#bit	TXB0D13		= TXB0D1.3
#bit	TXB0D12		= TXB0D1.2
#bit	TXB0D11		= TXB0D1.1
#bit	TXB0D10		= TXB0D1.0

// TXB0D0 Register
#bit	TXB0D07		= TXB0D0.7
#bit	TXB0D06		= TXB0D0.6
#bit	TXB0D05		= TXB0D0.5
#bit	TXB0D04		= TXB0D0.4
#bit	TXB0D03		= TXB0D0.3
#bit	TXB0D02		= TXB0D0.2
#bit	TXB0D01		= TXB0D0.1
#bit	TXB0D00		= TXB0D0.0

// TXB0DLC Register
#bit	TXB0RTR		= TXB0DLC.6	// TX frame remote transmission request
#bit	TXB0DLC3	= TXB0DLC.3	// data length code bits
#bit	TXB0DLC2	= TXB0DLC.2
#bit	TXB0DLC1	= TXB0DLC.1
#bit	TXB0DLC0	= TXB0DLC.0

// TXB0EIDL Register
#bit	TXB0EID7	= TXB0EIDL.7	// extended identifier bits
#bit	TXB0EID6	= TXB0EIDL.6
#bit	TXB0EID5	= TXB0EIDL.5
#bit	TXB0EID4	= TXB0EIDL.4
#bit	TXB0EID3	= TXB0EIDL.3
#bit	TXB0EID2	= TXB0EIDL.2
#bit	TXB0EID1	= TXB0EIDL.1
#bit	TXB0EID0	= TXB0EIDL.0

// TXB0EIDH Register
#bit	TXB0EID15	= TXB0EIDH.7	// extended identifier bits
#bit	TXB0EID14	= TXB0EIDH.6
#bit	TXB0EID13	= TXB0EIDH.5
#bit	TXB0EID12	= TXB0EIDH.4
#bit	TXB0EID11	= TXB0EIDH.3
#bit	TXB0EID10	= TXB0EIDH.2
#bit	TXB0EID9	= TXB0EIDH.1
#bit	TXB0EID8	= TXB0EIDH.0

// TXB0SIDL Register
#bit	TXB0SID2	= TXB0SIDL.7	// standard identifier bits
#bit	TXB0SID1	= TXB0SIDL.6
#bit	TXB0SID0	= TXB0SIDL.5
#bit	TXB0EXIDE	= TXB0SIDL.3	// extended identifier enable
#bit	TXB0EID17	= TXB0SIDL.1	// extended identifier bits
#bit	TXB0EID16	= TXB0SIDL.0

// TXB0SIDH Register
#bit	TXB0SID10	= TXB0SIDH.7	// stanadard identifier bits
#bit	TXB0SID9	= TXB0SIDH.6
#bit	TXB0SID8	= TXB0SIDH.5
#bit	TXB0SID7	= TXB0SIDH.4
#bit	TXB0SID6	= TXB0SIDH.3
#bit	TXB0SID5	= TXB0SIDH.2
#bit	TXB0SID4	= TXB0SIDH.1
#bit	TXB0SID3	= TXB0SIDH.0

// TXB0CON Register
#bit	TXB0ABT		= TXB0CON.6	// TX abort status
#bit	TXB0LARB	= TXB0CON.5	// TX lost arbitration status
#bit	TXB0ERR		= TXB0CON.4	// TX error detect
#bit	TXB0REQ		= TXB0CON.3	// TX request status
#bit	TXB0PRI1	= TXB0CON.1	// TX priority bits
#bit	TXB0PRI0	= TXB0CON.0

// CANSTATRO3 Register
#bit	OPMODE32	= CANSTATRO3.7
#bit	OPMODE31	= CANSTATRO3.6
#bit	OPMODE30	= CANSTATRO3.5
#bit	ICODE32		= CANSTATRO3.3
#bit	ICODE31		= CANSTATRO3.2
#bit	ICODE30		= CANSTATRO3.1

// TXB1D7 Register
#bit	TXB1D77		= TXB1D7.7
#bit	TXB1D76		= TXB1D7.6
#bit	TXB1D75		= TXB1D7.5
#bit	TXB1D74		= TXB1D7.4
#bit	TXB1D73		= TXB1D7.3
#bit	TXB1D72		= TXB1D7.2
#bit	TXB1D71		= TXB1D7.1
#bit	TXB1D70		= TXB1D7.0

// TXB1D6 Register
#bit	TXB1D67		= TXB1D6.7
#bit	TXB1D66		= TXB1D6.6
#bit	TXB1D65		= TXB1D6.5
#bit	TXB1D64		= TXB1D6.4
#bit	TXB1D63		= TXB1D6.3
#bit	TXB1D62		= TXB1D6.2
#bit	TXB1D61		= TXB1D6.1
#bit	TXB1D60		= TXB1D6.0

// TXB1D5 Register
#bit	TXB1D57		= TXB1D5.7
#bit	TXB1D56		= TXB1D5.6
#bit	TXB1D55		= TXB1D5.5
#bit	TXB1D54		= TXB1D5.4
#bit	TXB1D53		= TXB1D5.3
#bit	TXB1D52		= TXB1D5.2
#bit	TXB1D51		= TXB1D5.1
#bit	TXB1D50		= TXB1D5.0

// TXB1D4 Register
#bit	TXB1D47		= TXB1D4.7
#bit	TXB1D46		= TXB1D4.6
#bit	TXB1D45		= TXB1D4.5
#bit	TXB1D44		= TXB1D4.4
#bit	TXB1D43		= TXB1D4.3
#bit	TXB1D42		= TXB1D4.2
#bit	TXB1D41		= TXB1D4.1
#bit	TXB1D40		= TXB1D4.0

// TXB1D3 Register
#bit	TXB1D37		= TXB1D3.7
#bit	TXB1D36		= TXB1D3.6
#bit	TXB1D35		= TXB1D3.5
#bit	TXB1D34		= TXB1D3.4
#bit	TXB1D33		= TXB1D3.3
#bit	TXB1D32		= TXB1D3.2
#bit	TXB1D31		= TXB1D3.1
#bit	TXB1D30		= TXB1D3.0

// TXB1D2 Register
#bit	TXB1D27		= TXB1D2.7
#bit	TXB1D26		= TXB1D2.6
#bit	TXB1D25		= TXB1D2.5
#bit	TXB1D24		= TXB1D2.4
#bit	TXB1D23		= TXB1D2.3
#bit	TXB1D22		= TXB1D2.2
#bit	TXB1D21		= TXB1D2.1
#bit	TXB1D20		= TXB1D2.0

// TXB1D1 Register
#bit	TXB1D17		= TXB1D1.7
#bit	TXB1D16		= TXB1D1.6
#bit	TXB1D15		= TXB1D1.5
#bit	TXB1D14		= TXB1D1.4
#bit	TXB1D13		= TXB1D1.3
#bit	TXB1D12		= TXB1D1.2
#bit	TXB1D11		= TXB1D1.1
#bit	TXB1D10		= TXB1D1.0

// TXB1D0 Register
#bit	TXB1D07		= TXB1D0.7
#bit	TXB1D06		= TXB1D0.6
#bit	TXB1D05		= TXB1D0.5
#bit	TXB1D04		= TXB1D0.4
#bit	TXB1D03		= TXB1D0.3
#bit	TXB1D02		= TXB1D0.2
#bit	TXB1D01		= TXB1D0.1
#bit	TXB1D00		= TXB1D0.0

// TXB1DLC Register
#bit	TXB1RTR		= TXB1DLC.6
#bit	TXB1DLC3	= TXB1DLC.3
#bit	TXB1DLC2	= TXB1DLC.2
#bit	TXB1DLC1	= TXB1DLC.1
#bit	TXB1DLC0	= TXB1DLC.0

// TXB1EIDL Register
#bit	TXB1EID7	= TXB1EIDL.7
#bit	TXB1EID6	= TXB1EIDL.6
#bit	TXB1EID5	= TXB1EIDL.5
#bit	TXB1EID4	= TXB1EIDL.4
#bit	TXB1EID3	= TXB1EIDL.3
#bit	TXB1EID2	= TXB1EIDL.2
#bit	TXB1EID1	= TXB1EIDL.1
#bit	TXB1EID0	= TXB1EIDL.0

// TXB1EIDH Register
#bit	TXB1EID15	= TXB1EIDH.7
#bit	TXB1EID14	= TXB1EIDH.6
#bit	TXB1EID13	= TXB1EIDH.5
#bit	TXB1EID12	= TXB1EIDH.4
#bit	TXB1EID11	= TXB1EIDH.3
#bit	TXB1EID10	= TXB1EIDH.2
#bit	TXB1EID9	= TXB1EIDH.1
#bit	TXB1EID8	= TXB1EIDH.0

// TXB1SIDL Register
#bit	TXB1SID2	= TXB1SIDL.7
#bit	TXB1SID1	= TXB1SIDL.6
#bit	TXB1SID0	= TXB1SIDL.5
#bit	TXB1EXIDE	= TXB1SIDL.3
#bit	TXB1EID17	= TXB1SIDL.1
#bit	TXB1EID16	= TXB1SIDL.0

// TXB1SIDH Register
#bit	TXB1SID10	= TXB1SIDH.7
#bit	TXB1SID9	= TXB1SIDH.6
#bit	TXB1SID8	= TXB1SIDH.5
#bit	TXB1SID7	= TXB1SIDH.4
#bit	TXB1SID6	= TXB1SIDH.3
#bit	TXB1SID5	= TXB1SIDH.2
#bit	TXB1SID4	= TXB1SIDH.1
#bit	TXB1SID3	= TXB1SIDH.0

// TXB1CON Register
#bit	TXB1ABT		= TXB1CON.6
#bit	TXB1LARB	= TXB1CON.5
#bit	TXB1ERR		= TXB1CON.4
#bit	TXB1REQ		= TXB1CON.3
#bit	TXB1PRI1	= TXB1CON.1
#bit	TXB1PRI0	= TXB1CON.0

// CANSTATRO4 Register
#bit	OPMODE42	= CANSTATRO4.7
#bit	OPMODE41	= CANSTATRO4.6
#bit	OPMODE40	= CANSTATRO4.5
#bit	ICODE42		= CANSTATRO4.3
#bit	ICODE41		= CANSTATRO4.2
#bit	ICODE40		= CANSTATRO4.1

// TXB2D7 Register
#bit	TXB2D77		= TXB2D7.7
#bit	TXB2D76		= TXB2D7.6
#bit	TXB2D75		= TXB2D7.5
#bit	TXB2D74		= TXB2D7.4
#bit	TXB2D73		= TXB2D7.3
#bit	TXB2D72		= TXB2D7.2
#bit	TXB2D71		= TXB2D7.1
#bit	TXB2D70		= TXB2D7.0

// TXB2D6 Register
#bit	TXB2D67		= TXB2D6.7
#bit	TXB2D66		= TXB2D6.6
#bit	TXB2D65		= TXB2D6.5
#bit	TXB2D64		= TXB2D6.4
#bit	TXB2D63		= TXB2D6.3
#bit	TXB2D62		= TXB2D6.2
#bit	TXB2D61		= TXB2D6.1
#bit	TXB2D60		= TXB2D6.0

// TXB2D5 Register
#bit	TXB2D57		= TXB2D5.7
#bit	TXB2D56		= TXB2D5.6
#bit	TXB2D55		= TXB2D5.5
#bit	TXB2D54		= TXB2D5.4
#bit	TXB2D53		= TXB2D5.3
#bit	TXB2D52		= TXB2D5.2
#bit	TXB2D51		= TXB2D5.1
#bit	TXB2D50		= TXB2D5.0

// TXB2D4 Register
#bit	TXB2D47		= TXB2D4.7
#bit	TXB2D46		= TXB2D4.6
#bit	TXB2D45		= TXB2D4.5
#bit	TXB2D44		= TXB2D4.4
#bit	TXB2D43		= TXB2D4.3
#bit	TXB2D42		= TXB2D4.2
#bit	TXB2D41		= TXB2D4.1
#bit	TXB2D40		= TXB2D4.0

// TXB2D3 Register
#bit	TXB2D37		= TXB2D3.7
#bit	TXB2D36		= TXB2D3.6
#bit	TXB2D35		= TXB2D3.5
#bit	TXB2D34		= TXB2D3.4
#bit	TXB2D33		= TXB2D3.3
#bit	TXB2D32		= TXB2D3.2
#bit	TXB2D31		= TXB2D3.1
#bit	TXB2D30		= TXB2D3.0

// TXB2D2 Register
#bit	TXB2D27		= TXB2D2.7
#bit	TXB2D26		= TXB2D2.6
#bit	TXB2D25		= TXB2D2.5
#bit	TXB2D24		= TXB2D2.4
#bit	TXB2D23		= TXB2D2.3
#bit	TXB2D22		= TXB2D2.2
#bit	TXB2D21		= TXB2D2.1
#bit	TXB2D20		= TXB2D2.0

// TXB2D1 Register
#bit	TXB2D17		= TXB2D1.7
#bit	TXB2D16		= TXB2D1.6
#bit	TXB2D15		= TXB2D1.5
#bit	TXB2D14		= TXB2D1.4
#bit	TXB2D13		= TXB2D1.3
#bit	TXB2D12		= TXB2D1.2
#bit	TXB2D11		= TXB2D1.1
#bit	TXB2D10		= TXB2D1.0

// TXB2D0 Register
#bit	TXB2D07		= TXB2D0.7
#bit	TXB2D06		= TXB2D0.6
#bit	TXB2D05		= TXB2D0.5
#bit	TXB2D04		= TXB2D0.4
#bit	TXB2D03		= TXB2D0.3
#bit	TXB2D02		= TXB2D0.2
#bit	TXB2D01		= TXB2D0.1
#bit	TXB2D00		= TXB2D0.0

// TXB2DLC Register
#bit	TXB2RTR		= TXB2DLC.6
#bit	TXB2DLC3	= TXB2DLC.3
#bit	TXB2DLC2	= TXB2DLC.2
#bit	TXB2DLC1	= TXB2DLC.1
#bit	TXB2DLC0	= TXB2DLC.0

// TXB2EIDL Register
#bit	TXB2EID7	= TXB2EIDL.7
#bit	TXB2EID6	= TXB2EIDL.6
#bit	TXB2EID5	= TXB2EIDL.5
#bit	TXB2EID4	= TXB2EIDL.4
#bit	TXB2EID3	= TXB2EIDL.3
#bit	TXB2EID2	= TXB2EIDL.2
#bit	TXB2EID1	= TXB2EIDL.1
#bit	TXB2EID0	= TXB2EIDL.0

// TXB2EIDH Register
#bit	TXB2EID15	= TXB2EIDH.7
#bit	TXB2EID14	= TXB2EIDH.6
#bit	TXB2EID13	= TXB2EIDH.5
#bit	TXB2EID12	= TXB2EIDH.4
#bit	TXB2EID11	= TXB2EIDH.3
#bit	TXB2EID10	= TXB2EIDH.2
#bit	TXB2EID9	= TXB2EIDH.1
#bit	TXB2EID8	= TXB2EIDH.0

// TXB2SIDL Register
#bit	TXB2SID2	= TXB2SIDL.7
#bit	TXB2SID1	= TXB2SIDL.6
#bit	TXB2SID0	= TXB2SIDL.5
#bit	TXB2EXIDE	= TXB2SIDL.3
#bit	TXB2EID17	= TXB2SIDL.1
#bit	TXB2EID16	= TXB2SIDL.0

// TXB2SIDH Register
#bit	TXB2SID10	= TXB2SIDH.7
#bit	TXB2SID9	= TXB2SIDH.6
#bit	TXB2SID8	= TXB2SIDH.5
#bit	TXB2SID7	= TXB2SIDH.4
#bit	TXB2SID6	= TXB2SIDH.3
#bit	TXB2SID5	= TXB2SIDH.2
#bit	TXB2SID4	= TXB2SIDH.1
#bit	TXB2SID3	= TXB2SIDH.0

// TXB2CON Register
#bit	TXB2ABT		= TXB2CON.6
#bit	TXB2LARB	= TXB2CON.5
#bit	TXB2ERR		= TXB2CON.4
#bit	TXB2REQ		= TXB2CON.3
#bit	TXB2PRI1	= TXB2CON.1
#bit	TXB2PRI0	= TXB2CON.0

// RXM1EIDL Register
#bit	RXM1EID7	= RXM1EIDL.7
#bit	RXM1EID6	= RXM1EIDL.6
#bit	RXM1EID5	= RXM1EIDL.5
#bit	RXM1EID4	= RXM1EIDL.4
#bit	RXM1EID3	= RXM1EIDL.3
#bit	RXM1EID2	= RXM1EIDL.2
#bit	RXM1EID1	= RXM1EIDL.1
#bit	RXM1EID0	= RXM1EIDL.0

// RXM1EIDH Register
#bit	RXM1EID15	= RXM1EIDH.7
#bit	RXM1EID14	= RXM1EIDH.6
#bit	RXM1EID13	= RXM1EIDH.5
#bit	RXM1EID12	= RXM1EIDH.4
#bit	RXM1EID11	= RXM1EIDH.3
#bit	RXM1EID10	= RXM1EIDH.2
#bit	RXM1EID9	= RXM1EIDH.1
#bit	RXM1EID8	= RXM1EIDH.0

// RXM1SIDL Register
#bit	RXM1SID2	= RXM1SIDL.7
#bit	RXM1SID1	= RXM1SIDL.6
#bit	RXM1SID0	= RXM1SIDL.5
#bit	RXM1EID17	= RXM1SIDL.1
#bit	RXM1EID16	= RXM1SIDL.0

// RXM1SIDH Register
#bit	RXM1SID10	= RXM1SIDH.7
#bit	RXM1SID9	= RXM1SIDH.6
#bit	RXM1SID8	= RXM1SIDH.5
#bit	RXM1SID7	= RXM1SIDH.4
#bit	RXM1SID6	= RXM1SIDH.3
#bit	RXM1SID5	= RXM1SIDH.2
#bit	RXM1SID4	= RXM1SIDH.1
#bit	RXM1SID3	= RXM1SIDH.0

// RXM0EIDL Register
#bit	RXM0EID7	= RXM0EIDL.7
#bit	RXM0EID6	= RXM0EIDL.6
#bit	RXM0EID5	= RXM0EIDL.5
#bit	RXM0EID4	= RXM0EIDL.4
#bit	RXM0EID3	= RXM0EIDL.3
#bit	RXM0EID2	= RXM0EIDL.2
#bit	RXM0EID1	= RXM0EIDL.1
#bit	RXM0EID0	= RXM0EIDL.0

// RXM0EIDH Register
#bit	RXM0EID15	= RXM0EIDH.7
#bit	RXM0EID14	= RXM0EIDH.6
#bit	RXM0EID13	= RXM0EIDH.5
#bit	RXM0EID12	= RXM0EIDH.4
#bit	RXM0EID11	= RXM0EIDH.3
#bit	RXM0EID10	= RXM0EIDH.2
#bit	RXM0EID9	= RXM0EIDH.1
#bit	RXM0EID8	= RXM0EIDH.0

// RXM0SIDL Register
#bit	RXM0SID2	= RXM0SIDL.7
#bit	RXM0SID1	= RXM0SIDL.6
#bit	RXM0SID0	= RXM0SIDL.5
#bit	RXM0EID17	= RXM0SIDL.1
#bit	RXM0EID16	= RXM0SIDL.0

// RXM0SIDH Register
#bit	RXM0SID10	= RXM0SIDH.7
#bit	RXM0SID9	= RXM0SIDH.6
#bit	RXM0SID8	= RXM0SIDH.5
#bit	RXM0SID7	= RXM0SIDH.4
#bit	RXM0SID6	= RXM0SIDH.3
#bit	RXM0SID5	= RXM0SIDH.2
#bit	RXM0SID4	= RXM0SIDH.1
#bit	RXM0SID3	= RXM0SIDH.0

// RXF5EIDL Register
#bit	RXF5EID7	= RXF5EIDL.7
#bit	RXF5EID6	= RXF5EIDL.6
#bit	RXF5EID5	= RXF5EIDL.5
#bit	RXF5EID4	= RXF5EIDL.4
#bit	RXF5EID3	= RXF5EIDL.3
#bit	RXF5EID2	= RXF5EIDL.2
#bit	RXF5EID1	= RXF5EIDL.1
#bit	RXF5EID0	= RXF5EIDL.0

// RXF5EIDH Register
#bit	RXF5EID15	= RXF5EIDH.7
#bit	RXF5EID14	= RXF5EIDH.6
#bit	RXF5EID13	= RXF5EIDH.5
#bit	RXF5EID12	= RXF5EIDH.4
#bit	RXF5EID11	= RXF5EIDH.3
#bit	RXF5EID10	= RXF5EIDH.2
#bit	RXF5EID9	= RXF5EIDH.1
#bit	RXF5EID8	= RXF5EIDH.0

// RXF5SIDL Register
#bit	RXF5SID2	= RXF5SIDL.7
#bit	RXF5SID1	= RXF5SIDL.6
#bit	RXF5SID0	= RXF5SIDL.5
#bit	RXF5EXIDEN	= RXF5SIDL.3
#bit	RXF5EID17	= RXF5SIDL.1
#bit	RXF5EID16	= RXF5SIDL.0

// RXF5SIDH Register
#bit	RXF5SID10	= RXF5SIDH.7
#bit	RXF5SID9	= RXF5SIDH.6
#bit	RXF5SID8	= RXF5SIDH.5
#bit	RXF5SID7	= RXF5SIDH.4
#bit	RXF5SID6	= RXF5SIDH.3
#bit	RXF5SID5	= RXF5SIDH.2
#bit	RXF5SID4	= RXF5SIDH.1
#bit	RXF5SID3	= RXF5SIDH.0

// RXF4EIDL Register
#bit	RXF4EID7	= RXF4EIDL.7
#bit	RXF4EID6	= RXF4EIDL.6
#bit	RXF4EID5	= RXF4EIDL.5
#bit	RXF4EID4	= RXF4EIDL.4
#bit	RXF4EID3	= RXF4EIDL.3
#bit	RXF4EID2	= RXF4EIDL.2
#bit	RXF4EID1	= RXF4EIDL.1
#bit	RXF4EID0	= RXF4EIDL.0

// RXF4EIDH Register
#bit	RXF4EID15	= RXF4EIDH.7
#bit	RXF4EID14	= RXF4EIDH.6
#bit	RXF4EID13	= RXF4EIDH.5
#bit	RXF4EID12	= RXF4EIDH.4
#bit	RXF4EID11	= RXF4EIDH.3
#bit	RXF4EID10	= RXF4EIDH.2
#bit	RXF4EID9	= RXF4EIDH.1
#bit	RXF4EID8	= RXF4EIDH.0

// RXF4SIDL Register
#bit	RXF4SID2	= RXF4SIDL.7
#bit	RXF4SID1	= RXF4SIDL.6
#bit	RXF4SID0	= RXF4SIDL.5
#bit	RXF4EXIDEN	= RXF4SIDL.3
#bit	RXF4EID17	= RXF4SIDL.1
#bit	RXF4EID16	= RXF4SIDL.0

// RXF4SIDH Register
#bit	RXF4SID10	= RXF4SIDH.7
#bit	RXF4SID9	= RXF4SIDH.6
#bit	RXF4SID8	= RXF4SIDH.5
#bit	RXF4SID7	= RXF4SIDH.4
#bit	RXF4SID6	= RXF4SIDH.3
#bit	RXF4SID5	= RXF4SIDH.2
#bit	RXF4SID4	= RXF4SIDH.1
#bit	RXF4SID3	= RXF4SIDH.0

// RXF3EIDL Register
#bit	RXF3EID7	= RXF3EIDL.7
#bit	RXF3EID6	= RXF3EIDL.6
#bit	RXF3EID5	= RXF3EIDL.5
#bit	RXF3EID4	= RXF3EIDL.4
#bit	RXF3EID3	= RXF3EIDL.3
#bit	RXF3EID2	= RXF3EIDL.2
#bit	RXF3EID1	= RXF3EIDL.1
#bit	RXF3EID0	= RXF3EIDL.0

// RXF3EIDH Register
#bit	RXF3EID15	= RXF3EIDH.7
#bit	RXF3EID14	= RXF3EIDH.6
#bit	RXF3EID13	= RXF3EIDH.5
#bit	RXF3EID12	= RXF3EIDH.4
#bit	RXF3EID11	= RXF3EIDH.3
#bit	RXF3EID10	= RXF3EIDH.2
#bit	RXF3EID9	= RXF3EIDH.1
#bit	RXF3EID8	= RXF3EIDH.0

// RXF3SIDL Register
#bit	RXF3SID2	= RXF3SIDL.7
#bit	RXF3SID1	= RXF3SIDL.6
#bit	RXF3SID0	= RXF3SIDL.5
#bit	RXF3EXIDEN	= RXF3SIDL.3
#bit	RXF3EID17	= RXF3SIDL.1
#bit	RXF3EID16	= RXF3SIDL.0

// RXF3SIDH Register
#bit	RXF3SID10	= RXF3SIDH.7
#bit	RXF3SID9	= RXF3SIDH.6
#bit	RXF3SID8	= RXF3SIDH.5
#bit	RXF3SID7	= RXF3SIDH.4
#bit	RXF3SID6	= RXF3SIDH.3
#bit	RXF3SID5	= RXF3SIDH.2
#bit	RXF3SID4	= RXF3SIDH.1
#bit	RXF3SID3	= RXF3SIDH.0

// RXF2EIDL Register
#bit	RXF2EID7	= RXF2EIDL.7
#bit	RXF2EID6	= RXF2EIDL.6
#bit	RXF2EID5	= RXF2EIDL.5
#bit	RXF2EID4	= RXF2EIDL.4
#bit	RXF2EID3	= RXF2EIDL.3
#bit	RXF2EID2	= RXF2EIDL.2
#bit	RXF2EID1	= RXF2EIDL.1
#bit	RXF2EID0	= RXF2EIDL.0

// RXF2EIDH Register
#bit	RXF2EID15	= RXF2EIDH.7
#bit	RXF2EID14	= RXF2EIDH.6
#bit	RXF2EID13	= RXF2EIDH.5
#bit	RXF2EID12	= RXF2EIDH.4
#bit	RXF2EID11	= RXF2EIDH.3
#bit	RXF2EID10	= RXF2EIDH.2
#bit	RXF2EID9	= RXF2EIDH.1
#bit	RXF2EID8	= RXF2EIDH.0

// RXF2SIDL Register
#bit	RXF2SID2	= RXF2SIDL.7
#bit	RXF2SID1	= RXF2SIDL.6
#bit	RXF2SID0	= RXF2SIDL.5
#bit	RXF2EXIDEN	= RXF2SIDL.3
#bit	RXF2EID17	= RXF2SIDL.1
#bit	RXF2EID16	= RXF2SIDL.0

// RXF2SIDH Register
#bit	RXF2SID10	= RXF2SIDH.7
#bit	RXF2SID9	= RXF2SIDH.6
#bit	RXF2SID8	= RXF2SIDH.5
#bit	RXF2SID7	= RXF2SIDH.4
#bit	RXF2SID6	= RXF2SIDH.3
#bit	RXF2SID5	= RXF2SIDH.2
#bit	RXF2SID4	= RXF2SIDH.1
#bit	RXF2SID3	= RXF2SIDH.0

// RXF1EIDL Register
#bit	RXF1EID7	= RXF1EIDL.7
#bit	RXF1EID6	= RXF1EIDL.6
#bit	RXF1EID5	= RXF1EIDL.5
#bit	RXF1EID4	= RXF1EIDL.4
#bit	RXF1EID3	= RXF1EIDL.3
#bit	RXF1EID2	= RXF1EIDL.2
#bit	RXF1EID1	= RXF1EIDL.1
#bit	RXF1EID0	= RXF1EIDL.0

// RXF1EIDH Register
#bit	RXF1EID15	= RXF1EIDH.7
#bit	RXF1EID14	= RXF1EIDH.6
#bit	RXF1EID13	= RXF1EIDH.5
#bit	RXF1EID12	= RXF1EIDH.4
#bit	RXF1EID11	= RXF1EIDH.3
#bit	RXF1EID10	= RXF1EIDH.2
#bit	RXF1EID9	= RXF1EIDH.1
#bit	RXF1EID8	= RXF1EIDH.0

// RXF1SIDL Register
#bit	RXF1SID2	= RXF1SIDL.7
#bit	RXF1SID1	= RXF1SIDL.6
#bit	RXF1SID0	= RXF1SIDL.5
#bit	RXF1EXIDEN	= RXF1SIDL.3
#bit	RXF1EID17	= RXF1SIDL.1
#bit	RXF1EID16	= RXF1SIDL.0

// RXF1SIDH Register
#bit	RXF1SID10	= RXF1SIDH.7
#bit	RXF1SID9	= RXF1SIDH.6
#bit	RXF1SID8	= RXF1SIDH.5
#bit	RXF1SID7	= RXF1SIDH.4
#bit	RXF1SID6	= RXF1SIDH.3
#bit	RXF1SID5	= RXF1SIDH.2
#bit	RXF1SID4	= RXF1SIDH.1
#bit	RXF1SID3	= RXF1SIDH.0

// RXF0EIDL Register
#bit	RXF0EID7	= RXF0EIDL.7
#bit	RXF0EID6	= RXF0EIDL.6
#bit	RXF0EID5	= RXF0EIDL.5
#bit	RXF0EID4	= RXF0EIDL.4
#bit	RXF0EID3	= RXF0EIDL.3
#bit	RXF0EID2	= RXF0EIDL.2
#bit	RXF0EID1	= RXF0EIDL.1
#bit	RXF0EID0	= RXF0EIDL.0

// RXF0EIDH Register
#bit	RXF0EID15	= RXF0EIDH.7
#bit	RXF0EID14	= RXF0EIDH.6
#bit	RXF0EID13	= RXF0EIDH.5
#bit	RXF0EID12	= RXF0EIDH.4
#bit	RXF0EID11	= RXF0EIDH.3
#bit	RXF0EID10	= RXF0EIDH.2
#bit	RXF0EID9	= RXF0EIDH.1
#bit	RXF0EID8	= RXF0EIDH.0

// RXF0SIDL Register
#bit	RXF0SID2	= RXF0SIDL.7
#bit	RXF0SID1	= RXF0SIDL.6
#bit	RXF0SID0	= RXF0SIDL.5
#bit	RXF0EXIDEN	= RXF0SIDL.3
#bit	RXF0EID17	= RXF0SIDL.1
#bit	RXF0EID16	= RXF0SIDL.0

// RXF0SIDH Register
#bit	RXF0SID10	= RXF0SIDH.7
#bit	RXF0SID9	= RXF0SIDH.6
#bit	RXF0SID8	= RXF0SIDH.5
#bit	RXF0SID7	= RXF0SIDH.4
#bit	RXF0SID6	= RXF0SIDH.3
#bit	RXF0SID5	= RXF0SIDH.2
#bit	RXF0SID4	= RXF0SIDH.1
#bit	RXF0SID3	= RXF0SIDH.0
*/
#define EEPROM_SIZE	256

// Configuration Bit Values

// config. register 1
#define CONFIG1H	0x300001
// oscillator system clock switch
#define OSCSEN		0xDFFF	// enable
#define OSCSDIS		0xFFFF	// disable
// oscillator configuration types
#define RCRA6		0xFFFF	// RC with osc2 = RA6
#define HSPLL		0xFEFF	// HS with PLL enabled
#define ECRA6		0xFDFF	// EC with osc2 = RA6
#define ECDB4		0xFCFF	// EC with osc2 = div by 4 clk out
#define RC		0xFBFF
#define HS		0xFAFF
#define XT		0xF9FF
#define LP		0xF8FF

// config. register 2
#define CONFIG2L	0x300002
#define CONFIG2H	0x300003
// power-up timer
#define PWRTEN		0xFFFE	// enable
#define PWRTDIS		0xFFFF	// disable
// brown-out reset voltage
#define BORV20		0xFFFF	// 2.0 volts
#define BORV27		0xFFFB	// 2.7 volts
#define BORV42		0xFFF7	// 4.2 volts
#define BORV45		0xFFF3	// 4.5 volts
// brown-out reset enable
#define BOREN		0xFFFF	// enable
#define BORDIS		0xFFFD	// disable
// watchdog postscale
#define WDTPS128	0xFFFF	// 1:128
#define WDTPS64		0xFDFF	// 1:64
#define WDTPS32		0xFBFF	// 1:32
#define WDTPS16		0xF9FF	// 1:16
#define WDTPS8		0xF7FF	// 1:8
#define WDTPS4		0xF5FF	// 1:4
#define WDTPS2		0xF3FF	// 1:2
#define WDTPS1		0xF1FF	// 1:1
// watchdog timer
#define WDTEN		0xFFFF	// enable
#define WDTDIS		0xFEFF	// disable

// config. register 4
#define CONFIG4L	0x300006
// background debugger
#define DEBUGEN		0xFF7F	// enable
#define DEBUGDIS	0xFFFF	// disable
// low voltage ICSP
#define LVPEN		0xFFFF	// enable
#define LVPDIS		0xFFFB	// disable
// stack full/underflow reset enable
#define STVREN		0xFFFF	// stack full/under will cause reset
#define STVRDIS		0xFFFE	// stack full/under will not cause reset

// config. register 5
#define CONFIG5L	0x300008
#define CONFIG5H	0x300009
// general code protection
#if defined(_18F258) || defined(_18F458)
#define CPALL		0x3FF0	// protect all blocks (incl. boot, data, config)
#define CPA		0xFFF0	// protect 00200-07FFFh
#define CP3		0xFFF7	// protect 06000-07FFFh
#define CP2		0xFFFB	// protect 04000-05FFFh
#elif defined(_18F248) || defined(_18F448)
#define CPALL		0x3FFC	// protect all blocks (incl. boot, data, config)
#define CPA		0xFFFC	// protect 00200-07FFFh
#endif
#define CP1		0xFFFD	// protect 02000-03FFFh
#define CP0		0xFFFE	// protect 00200-01FFFh
#define UNPROTECT	0xFFFF	// unprotected code
// protect EEPROM data
#define CPD		0x7FFF	// protect EEPROM data
// protect boot block
#define CPB		0xBFFF	// protect boot code 00000-001FFh

// config. register 6
#define CONFIG6L	0x30000A
#define CONFIG6H	0x30000B
// write protection
#if defined(_18F258) || defined(_18F458)
#define WPALL		0x1FF0	// protect all blocks (incl. boot, data, config)
#define WPA		0xFFF0	// 00200-07FFFh write protected
#define WP3		0xFFF7	// 06000-07FFFh write protected
#define WP2		0xFFFB	// 04000-05FFFh write protected
#elif defined(_18F248) || defined(_18F448)
#define WPALL		0x1FFC	// protect all blocks (incl. boot, data, config)
#define	WPA		0xFFFC	// protect 00200-03FFFh
#endif
#define WP1		0xFFFD	// 02000-03FFFh write protected
#define WP0		0xFFFE	// 00200-01FFFh write protected
// unprotect
#define WPU		0xFFFF	// write enabled
// write protection EEPROM data
#define WPD		0x7FFF	// write protect EEPROM data
// write protection boot section
#define WPB		0xBFFF	// write protect boot section
// write protection configuration registers
#define WPC		0xDFFF	// write protect config. regs

// config. register 7
#define CONFIG7L	0x30000C
#define CONFIG7H	0x30000D
//  table read protection
#if defined(_18F258) || defined(_18F458)
#define PTBRALL		0xBFF0	// protect all blocks (incl. boot)
#define PTBRA		0xFFF0	// protect 00200-07FFFh from table reads in other blocks
#define PTBR3		0xFFF7	// protect 06000-07FFFh from table reads in other blocks
#define PTBR2		0xFFFB	// protect 04000-05FFFh from table reads in other blocks
#elif defined(_18F248) || defined(_18F448)
#define PTBRALL		0xBFFC	// protect all blocks (incl. boot)
#define PTBRA		0xFFFC	// protect 00200-03FFFh from table reads in other blocks
#endif
#define PTBR1		0xFFFD	// protect 02000-03FFFh from table reads in other blocks
#define PTBR0		0xFFFE	// protect 00200-01FFFh from table reads in other blocks
// boot section
#define PTBRB		0xBFFF	// protect boot section from table reads in other blocks
// unprotect
#define PTBRU		0xFFFF	// no protection from table reads in other blocks

// Alternative notation
#if defined(_18F258) || defined(_18F458)
#define TRPA		0xFFF0		// Protect All Blocks excluding Boot
#define TRPALL		0xBFF0		// Protect All Blocks including Boot
#define TRP3		0xFFF7		// Protect Block 3 (6000-7FFF)
#define TRP2		0xFFFB		// Protect Block 2 (4000-5FFF)
#elif defined(_18F248) || defined(_18F448)
#define TRPA		0xBFFC		// Protect All Blocks including Boot
// alternate definition for consistency
#define TRPALL		0xBFFC		// Protect All Blocks including Boot
#endif
#define TRP1		0xFFFD		// Protect Block 1 (2000-3FFF)
#define TRP0		0xFFFE		// Protect Block 0 (0000-1FFF)
#define TRPB		0xBFFF		// Protect Boot Block
#define TRU		0xFFFF		// Unprotected
